ʶһѵ¡ͧԻСҧ

4040 (Year 1971)

8080 ,Zilog Z80, Z-8000 (1974)

Intel 8086 ,IBM 's choice (1978)

AMD 29000 ,Aflexible register set(1978)

Motolola 8800, late elegant (Mid 1988)

CPU 860

<wbr>MOTOROLA 68000

<wbr>IBM RS/6000 Power chip (1990)

<wbr>DEC Alpha (1992)

4004 (Nov 1971)
Ẻ 4 bit ѺͧԴŢ 4 bit instruction 8 bit ǹ¡ҡǹ 1 K bit PC Ҵ 12 bit Ѻ Ҵ4 K (ٻẺ stack 4 Ѻ CALL RET) register ʧҴ 4 bit 16 register

8080 (1974)

8008 Сͺ PC Add Ҵ 14 bit address bus Ҵ 16 bit data bus Ҵ 8 bit ǹСͺ register Ҵ 8 bit ӹǹ 7 (A,B,C,D,E,H,L) stack poiter Ҵ 16 bit stack Ҵ 8 PC Ҵ 16 bit I/O port ҡ֧ 256 port

Zilog Z-80

Ѳҡ 8080 Ẻ 8 bit address Ҵ 16 bit öء opcode ͧ 8080 ա 80 ش شҴ 1,4,8 16 bit شͧ register 2 ͡ҡѧкԺѵǴ interrupt z80 register index 2 ǣ IX,IY interrupt ѡɳǡ relocate ҹ ѵ clock ͧ z-80 = 2.5 MHz Z-80-H = 6MHz

Zilog Z-8000 ,another direct competitor

z-8000 ѧҡ 8086 ҹ ԷҾ processor Ҵ 16 bit ö address ֧ 23 bit register Ẻ segment ( 7 bit Z-8000 register Ҵ 16 bit ӹǹ 16 Ҵ register register 8 á ͧ Z-8000 ö register Ҵ 8 bit ӹǹ 16 (˹ RH0,RL0,RH1,....) 16 ö register Ҵ 32 bit ӹǹ 8 register ʧ register 15 stack pointer ,register 14 stack segment (ͧ register ҧԧ 35 bit (RR214)) شẺ 32 bit öٳ( 64 bit) Ŵŧ Z-800 áẺ 2 áѺк OS(Operating System) աѺ ͧǹѺ&eacut e;͹ǹѺ͹ǡѺ ; interrupt ǹͧҺ Z-800 ǧ Refresh RAM ѵѵ ҧҹ ҡ feature ҧ Ѵ Z-8000 ѡ 1986 CPU 32 bit MC68020 Intel 80386 Z-80000 Z-80000 ֧ 32 bit Ѻ addressing mode ͧ Z-8000 segment addressing ҡ 24 bit ѧ MMU( CPU 68020 ŧ 68030) chip 16 line 256-byte ҹҹѺ cache ҧ Z-80000 ŵô ˹ memory pages ͡ҡѧ coprocessor ҹͧ data bus ͡Ѻ CPU Z-8000 ҹ pipeline (6 stage) pipeline ҧ 80486 68040 ͡ 1991

INTEL 8086 , IBM S CHOICE (1978 )

鹵ը( ٳ 16 Ի4Ե )ʹ ˵ͧʺͧʹͧʹԵҨ 2 ѹҧ memory location ѹ 2 ҧѹ memory location ѹ١ӡѴè 64 亵дɰѧʺѭ ҧҹ
֧ѺѺҧǺҧó ٧ʺѭ near/far pointerѧ ҹ address ҡ 80286 Ե͡ 1982 ͡ 32 Ե ( Ԫҡ Real ѧ Protected ԪѺѧͧ bug 80286 ͹ѧͧѡ ) ͧӹǹͧҧҡ selecter Ҵ 16 ԵѺ segment descriptor è location ʹҴ 24 Ե , Ҵ( ѧ 64K ) سѵ ( Vertual Memory support) ͧ segment
֧ memory ѧ١ӡѴ 64K segments з 80386 Ե͡ 1985 ֧Ѳ addressing : base reg + index reg * scale ( 1,2,4 8 Ե ) + displacement ( 8 32 bit constant = 32 bit address ( ٻͧ paged segme( ը좹Ҵ 16 Ե 6 ) ¡ѺС IBMS / 360 ͹ѺС Motorola 68030 ) Processor ੾( ֧¡ paged segmented ) ʹͧѺ͡͹ ԧ١ͧѺ code ١¹Ѻ 8008 ö run Pentium Pro 80386 MNU security modes ( ¡ ring ͧ system services,application services,application ) ѧ opcode ٻ¡ Z-80
80486 Ե͡ 1989 pipelines ҧó ᤪ 8K ԻѺ FPU (ҹͧ eight elemant 80- Ե-Orientted FPU 80387 FPU ) clack 2 ( Z-280 ) Ե͡ 1993 Ẻ Superscalar ( 1 integer unit Singel FPU ) Ѻ¡ 8K I/D ᤪ
᷹ 80586 586 öͧѹѷ ͡¹ ԧ Pentium ѡɳ¡Ѻ CPU ҡ NexGen Nx586 Ե͡ 1995 80x86 cloned processors ҡش ҡ NEC V20/ V30( cloned 8088/8086 ( ö run 8085 AMD Cyrix clones ͧ 80386 80486 ֧ Pentium
ʶһѵ¡͹ compatible CPU ͧ( Nx586 / Nx686, AMD K5 ) Pentium Pro clone ྐྵ¹Ẻ Hardware Decoder ¹ѧ RISC ( Executed RISC cores ྐྵ ( Cyrix / IBM 6x86 Ե͡ǧ 1996 ѧ executed ͧ 80x86 2 pipelines ͹Դ IBM ѧѲ?ŧѺ Power PC CPU Power PC 615 ԡ
ա˹ P6 1 2 Ի( CPU plus 256K 512K L2 cache - L/d L1 cache( ѹ 8 亵 ) CPU Super piplined processor Сͺ 3 decoder ( complex instruction 1 , simpler ones 2 ) ˹ŧ 80x86 Micro-Ops ( one per simpler decoder + Up to four from the complex decoder = three to six per cycle ) 5 micro ops 3 öԴк Parallel order ( 6 unit - FPU , 2 integer , 1 load/store ) 80x86 instruction Ҩҧ micro-ops CPU ¡Ѻ Nx586 AMD K5 йѵ ԧʺѭҹ Handing instruction ҧҧ Pentium Pro ¹Ҵ 16 Ե execute
AMD K5 ŧ 80x86 code ROPS ( RISC Operation ) execute ҹͧ RISC core Superscalar AMD 29K ֧ 4 ROPs ö֧ 6 units ( 2 integer , 1 FPU , 2 load/store , 1 branch unit ) 5 öʴ Ѻ͹ѭҳԡѺ K5 AMD ԢԷ NexGen Ѻ K6
NexGen / AMD Nx586 Ե͡ǧ 1994 ö execute micro-ops ( RISC86 code ) ҡͧ١¹ RISC86 ҡѺ x86 program ѡɳͻͺ 16K I/D L1 cache 2 , L2 cache bus ( ¡Ѻ Pentium Pro 2- Chip module )
Nx586 ʺ K6 ( Ե͡ 1996 ) Сͺᤪ 3 32K Ѻ ա 16K Ѻè decode ѧ FPU chip Ѵ cache bus ͧ Nx586 ҧѧٻ pin աѧ compatible Ѻ P54C model Pentium ǹ decoder 2 complex decoder ҧҡ Pentium Pro 1 complex decoder 2 simple decoder micro -ops ҡ 4 6 ( ѧ 7 unit - load , store , complex/simple integer , FPU , branch , multimedia )
AMD Ѻ͹حҵҡ MMX ( Matrix Math eXtension ) Ե CPUs ҧ Intel ѧѲ Pentium Pentium Pro MMX ѡɳ֧Ѻ SPARC VIS HP-PA MAX MMX instruction ʴѴ integer ͧ 8 , 16 ,32 , bit word 80 bit FPU stack 64 bit register 8 ( Ԫҧ FPU MMX ͧ ѹҡ stack MMX register ѹ Cyrix clones ͧ instruction ҧ M2 CPU
Intel ͡Ѻ Hewlett-Packard Ѳ Processor Ҵ 64 Ե compatible Ѻ 80x86 ŧ coprocessor ҹͧ Very Long Instruction Word Ҩ͡Դ

AMD 29000 , A flexible register set (1987)

AMD 29000 RISC CPU ա˹Ѳҡ Berkeley RISC ( ਤͧ IBM 801) ѹ 29000 ͹Ẻ bitslice ( Ե͡ҧ 1981 ) ֧Ѻ SPARC ͡ѧҡҹ 29000Сͺͧ register ˭ҡ Local Grobal set ҧ 29000 ͡Ҩ˹͹ SPARC Ѵҧҹ register
29000 Сͺ 64 grobal register SPARC 8 ա allocate Ҵͧѧҡ 128 ը stack cache Ѻ Stcak Fram ١͡ stack pointer( ͧ ISAR regisler Fairchild F8 CPU ) callers frame current frame ¡Ѻ Spill Fill Դǹͧ ᤪ ը loaded/saved ͧ˹õҴͧԹҡ 1 ֧ 128 ը״˭ͧ źը ը¡ SPARC
͹Ԫ⤴ը ըѡ ҧ͹Ԫ⤴ѧ١ѡ֧ҧͧѺ͹ҡ ˹Ҩͧ͹ fetch Ѻ( burth ) йáͧ ͹ᤪѴᤪ branch ( 16 ) ǹ cache supplies instruction ǧ֧˹
ը١ saved ҧԹѾ ӤѭͧԹѾͧԴ ҧ֧ ѧ֧ͧѴٻͧǺ֧ը ըöͧѹ  㹺ͧ͡ 4 ҡ֧ 29000 öªѺͺप蹵ҧ ١ҹ Processor ҡش ҧ׹ѹ ҷ RISC Processor ֧Ѻ٧ش 29000 MMU ѧʹѺʹع 29027 FPU , Superscalar 29050 Ե͡1990 FPU ͡ 4 instruction ö execute Out of order Speculatively
ǧ 1995 ѷ Advanced Micro Devices ԡѲ 29K ªҡ clones ͧ Intel 80x86 processor ֧Ѳ superscalar ҡԵ AMD 29000 FPU ( ͡ҡ 29050 ) shared Ѻ K5 ( ͡ 1995 ) processor compatible Ѻྐྵ ( K5 öŧͧ 80x86 RISC

Motolola 8800,late but elegant(Mid 1988)

Motolola 88000 ͡Ѵҡ 78000 Processor Ҵ 32 Ե ѧ˹ Processor ͧá ͧẺ RISC ҹ CPU ҡ Harvard Architecture ( ¡Ѻ Fairchild / Intergraph Clipper C100 (1986))кʨᤪ¡ѹѧ ֧ Դѹ Ѻǹ֧ ʶһѵ¡ͧ Hewlett Packard Precision ( HP / PA ) ͡ ըѺǺʶҹҡ Ǻ ֧ 88000 ҧҡ شҴ Segment addressing ӡѴ addressing 32 Ե ᷹ 64 Դѧ88200 MMU unit ᤪ ( multiprocessor ) ѧ MMU Ѻ CPU 88100 ( ¡Ѻ Clipper ) ǹ 88110 ᤪ MMU Ի
88000 Сͺ user register Ҵ 32 Ե 32 , 8 distinct internal - ALU ٹԷӹǹԧ ( single register set ѹ ) 88100 ALU Ѻٳ FPU Unit ( Сͺը FPU Ҵ 80 Ե 30 ) 88110 ҿԡ bit unit ١ pack unpack 4 , 8 ,16 Եӹǹ( pixels ) èŧ 32 bit word Ե͡Ѻ ҡѺ MIPS HP processor
88000 processor ѹѧк pipeline ( Ѻ interlocks ) ҧ˹ 88110 ALU öѧŶѴ Loaded / Saved 88110 ӡѺѿ ѧ processor ֧ͧ ¡Ŵ ˹ ͧѹ֡͹

CPU 860

CPU 860 ҡҹ ҡ scaler mode ֧ superscelar mode (ͧ ö) cach Ҵ 8k ӡѴ vector register Ҵ ( supercomputers) cache ͡˹ҡ address ͹ ᷹Ҿ data bus ¡ ҡѹ 4G Ѻ˹ Ẻ segment˹Ѵ˹ Ѻ ͹ 860 register Ҵ 32 bit ӹǹ 32 register Ẻ floating point 32 bit ӹǹ 32 860 microprocessor á FPU ,integer ALU 3-D graphic unit (ԴѺ FPU) ѺҴ

Motorola 68000

68000 16 32-bit register ¡ data address registers 1 address registerѺ stack pointer data registers öѺ operation ҧСͺ ͺҡ address register ͹ҡ address ͧ operation address register ١ӡѴ move , add / subtract load ҡ address operations ͹Ѻ CPU ѹ 68000ö fetch Ѵ execution ( 2 stage pipeline ) 6800032bitsunits Ǵ ö¡ forced segmentation ١͡ѺСͺ к´Ѻ floating point string
chip Сͧ Motolora
1.68000 16 32-bit register ¡ data address registers 1 address register Ѻ stack pointer data registers öѺ operation ҧ Сͺ ͺҡ address register ͹ҡ address ͧ operation address register ١ӡѴ move , add / subtract load ҡ address 68000 32 bits units Ǵ ö¡ forced segmentation ١͡Ѻ Сͺ к´Ѻ floating point string operations ͹Ѻ CPU ѹ 68000 ö fetch Ѵ execution ( 2 stage pipeline )
2.68010 virtual memory support special loop mode ( small decrement-and-branch loopsö executed ҡ instruction fetch buffer . )
3.68020 ( 1984 ) external data address bus 32 bits 256 byte cache 68030 MMU chip ǹ
4.68040 ( 1991 ) fully cache Harvard busses ҡ data instructions 6 stage pipeline chip FPU
5.68060 (1994) ͡ superscalar version ͹ Intel pentium NS320xx (Swordfish) series Դ͹͹ NX586 ,AMD K5 "Intel Pentium PRO" stage 3 ͧ 10-stage 68060 pipeline ŧ 680x0 decode RISC resource renaming reorder ѧ Branch cache branch decoded instruction stream ͹ AT&T Hobbit ҡ Processor ҹ
͡ҡ 68060 ѧСͺ ¹ŧ Power-saving ҡʴ ѧ Power дѺ 68040 ¹ŧ simple register-register instruction Դҡ address address stage ALU execute 2 cycle ͹

IBM RS/6000 POWER CHIP ( 1990 )

IBM ѴԹҴ work station ( ѧҡʺ稡Ѻ PC/RT ҹ ROMP processor ) ͡Ẻ CPU ҹǹͧç 801 ءԡ ɮ RISC RISC ҹѺŴش ( Reduced Instruction Set Computer ) IBM ¡ Reduced Instruction Set Cycles кǹѺ͹ͧ processor Ѻ high level instruction ҡ CISE processor ش CPU ( power 1 ) ͹ Сͺ 5 7 ǹ
1. branch unit
2. point unit
3. floating point unit
4. 2. 4. cache chips ( ¡ data instruction cache )
ҧ POWER PC Version ( ѺѲѹҧ IBM Apple MOTOROLA MOTOROLA 68000 Intel 8086 ) cache chip ( 32 k 601 ) version ¡ I/D caches. POWER PC Version ѧ ( simplified instruction set ) Ѻ
ǹͧ branch unit ͧ CPU enables multiple instruction executed 1 Сͺ͹ register , loop register performs branches code condition register 8 ǹ ( POWER 1. ʧǹ 2. Ѻ fixed floating point units, ա 6 ǹ öǹ ( ҡ ) öǨͺ ѧ multiple instructions (͡ҡѴ ) ǹͧ executing Ѻ͹ ( complex instruction )
ǹͧ branch unit öҴ¡ ԡ ö¡ǹ branch unit ѧѴáѺ procedure call returns program counter stack zero-cycles calls ͹ѺѹѺ شѧѴá interrupt ҡáͧ software
The integer unit ˹ٻ operation ͧ integer load stores POWER1 POWER PC 601 ( version ѧǹ concurrent ˹ load/store ) ء version Сͺ register 32 bit POWER PC 620 AS register 64 bits high end POWER PC-AS شѺ AS/400 minicomputer series ѧ֧ŢԵҹ? ; ǡѺѡ ѹѺ matrix coprocessor ˹ŢöѾ&c edil; subsequent instructions ͧ ͹¹ʶҹԴк&Ogra ve; version ѧСͺ register ١ rename ѺҴ͡ҡѴ&Ecir c; execution Ѵҧ¹ ѹͺѺ ش reorder з ˹ͧ branch/dispatch ͧ rename register ͧ integer floating point
˹ͧ floating point ѧСͺ thirty two 64 bit register ˹Դͧ floating point operations Сͺ multiply/accumulate array multiply ǡ register ١ load store ˹شȹ POWER1 POWER PC601 ˹ͧ load/store FPU ѧСͺ rename register ͹ҧ CPU floating point trap ѧѴ͹ pipelining-normally. Traps bit set ͧѺŢȹ software öǨͺ͹˹ trap ص software-operation Ѻ debugging ѧ slower precise trap mode ա
Data bus ҡ 32 bit 256 bit ö 6 4 load store ѹ POWER PC 601 MOTOROLA 88000 microprocessor bus ҡ version Ѩغѹ POWER PC ˹ bus ੾ ҧѺ 128 bit back side bus ֧ L2.cache
IBM POWER CPU ԷҾ Դ֧͡Ẻ mainframe سѵ͹ " weird and Innovative " ѧ RISC ͹٧ ԷҾ ͧ˹ clock rate ͧ͡͹
clock rate ٧ ѺѲҡ Exponential Technology Դͧ෤ Intel ֧ Pentium Pentium Pro CPU ѹ Embedded version ѧѺҡ IBM MOTOROLO

DEC Alpha ͡Ѻ͹Ҥ (1992)

ʶһѵ¡ͧ DEC Alpha Ѻ͡ DEC ѺԹԵ 25 ¹ŧѡ PAL calls ( set writable ͹ ) ѧѺҹͧѡɳ Ǻ͹ͧ سѵ˹Ѵਹ chip ͧ Alpha á 21064 Alpha ʶһѵ¡ 64 bit ( 32 bit instruction ) ʹѺʹع 8- 16-bit ͧԹ ͧ¹ŧ ѧ֧ function ٭ Alpha 32 bit Թҧҡ 64 bit §ͧѹ overflow Alpha ö ͡ҡѧسѵ͹ MIPS R2000 Сͺ register ˹͹ ҧ Alpha ѧ interlocked pipeline ѧ֧ register Ѻ ٳ / Alpha ѧ֧ա§ѭѡɳ& agrave;ԺǹѺ͹ С R2000 ͧѲ R8000 R10000 ͧ Alpha ʶһѵ¡ DECs two prior MIPS ҹͧ workstation VAX minicomputer chip öѴ IEEE VAX32 64 bit floating point operation ѡɳͧ Privileged Architecture Library ( PAL) ¡ set ͧ programmable ( interruptable ) ¹ش Alpha programmable Ҵͧ western Digital MCP-1600 AMD Am 2910 CPUs ¹ŧ ҡش binary translator ( ŧẺ亹 ) ʹѺʹع operating system ҡ Alpha ѧѺ͡͹&curr en;Ѻ 1000-fold سѵ& curren; ش superscalar Ѻ reorder trap ͹ Ѵ syncronise Դͧ branch delay slot ͹ R2000 Եѭҧ superscalar execution ѭ compatibility Ѻ extended pipeline ᷹ speculative executive branch cache chip 21064 ѺѺ 1. integer 2. Floating point 1 load / store unit 21164 ( ͹ 1995 ) 1. integer / load / store unit Ѻ byte vector 1. Floating point unit clock speed ҡ 200 MHz 300 MHz ѺԴ 1. level 2. Cache chip 21264 4 integer unit , 2 different floating point unit Ѻö load 4 ,dispatch 6 retire eight instruction cycle ö֧ 500 MHz ,Multimedia 21264 simple Сͺ VIS-type motion estimation ( MPEG )


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