RAM (Random Access Memory) 

˹֧ ͧѺ (Sequential Access) ͧ ˹ Address (Ţк˹) Ѻ RAM Memory Chip ѹͧ 2 ˭
                1.SRAM(Static RAM)
                2.DRAM(Dynamic RAM)
سѵҧѹ ҧ SRAM Ѻ DRAM SRAM Ҥ٧ ͧҡ SRAM ٧ DRAM
ҹ RAM ͧ§ʹ ͡ҡ§ DRAM ѧͧ Refresh ͹͹ç ԴѺ SRAM ͧ Refresh ͧҡ DRAM ҡ MOSѡ ͧШ ҹ Ш͡ ͧ Refresh Шʹҹ ǹ SRAM ҡ Flip-Flop ͧ Refresh SRAM Թҡ DRAM ѹͧҡ Flip-Flop ͧ

ͧ RAM Դѹҧ

Memorychip Ţ HM411000-70 Ţѧ (-) Ţ͡ ͧ RAM Ţ ¡ Accesstime ֧ ʴ ١ ͡ҧ Data bus˹ Access time ʴ RAM ҡ

ҧ Access time Chip

Access time(ns) 
Ţ Memory chip
250 
25
200
20
150
15 
120
12
100
10
85 
85
80 
8,80
70
7,70
65
65
60
6,60
53
53

ͧ RAM ¡ Cycle time ˹ ns Cycle time ҡѺ Read/Write cycle time (ѭҳԴ ҹ/¹ RAM) Ѻ Access time Refresh time
RAM ͧͺʹͧ CPU 2 clock cycle 2 Һ ҡ RAM ͺʹͧѹ RAM ѭҳ /WAIT ͡ CPU CPU clock cycle ǧ¡ WAIT STATE

Ը WAIT STATE
    1. ෤Ԥ INTERLEAVE
                ෤ԤŴѭͧ Refresh time ҹͧ RAM Դ͡Ѻ Memory 1 address 1 cycle time CPU Դ Ѻ Memory Դ block Address §ѹ ҡԧ ෤Ԥ Interleave ֧Դ ѡ Cycle time ѹԴ Cycle time ŧ
                Ѻ Bank ͧ Memory Bank ͡˹ Memory address Ţ ա Bank Ţ CPU ԴѺѺ 2 Bank йͧ Memory Bank ӹǹ 2 Bank 4 Bank Memory Ҵѹ Memory Bank ҹ Memory 2 Bank Bank

    2. Ը Page Mode
                Ըͧ RAM Paged RAM Memory ١ͧ Page Page Դ͡Ѻ Memory Address Page ѹ ͧ Wait State Դ͡Ѻ Page Wait State ͹

    3. Cache Memory Memory
                ǹ١Ѻ CPU Internal Cache Դ ¡ External Cache RAM ͧ ٧ҡ Wait State Ը CPU Դ͡Ѻ Cache SRAM ٧͹ WaitState ǧ Cache controller Ѵ Cache ѹѴ ͡ҡ main memory ҳ͡ 2-4 KB Cache CPU Դ Memory Cache ͹ͧ ҡ Main memory Ӥѭͧ Cache Ѵ͡١ͧͧ CPU Cache controller Ը Random Random ҧѡ CPU ѡͧ ͧѹ й Cache Ѵ͡Ѵ Random Ẻ֧ 80% Wait State 80% ͧ ҹ

Check Parity
        Parity Եա 1 Ե Ѻء 8 Ե ͧ 9 Ե Ե Ǩͺ ԴҴ ѡѺӹǹԵ 1 ء 8 Ե Parity 2 Ը Odd Parity (Parity ) Even Parity (Parity)
        ѺԸ Odd Parity ѺӹǹԵ 1 8 Եӹǹ IC 74LS280 ˹ҧ Parity Ǩͺ 74LS280 Ѻӹǹ 1 8 Ե ӹǹ Parity bit ١ 1 ӹǹͧ 1 9 Ե ( Parity bit ) ӹǹ Ѻӹǹͧ 1 8 Ե Ţ Parity bit ١ 0 ӹǹͧ 1 9 Ե Ţ Ը Even Parity Ѻѹ Parity ӹǹͧ 1 9 Եӹǹ
        Parity bit ١ҧ͹ ¹ŧ RAM ١Ǩͺ ҹҡ RAM 11001010 Ը Odd Parity Parity bit 1 ͹ҹԴ¹ŧ 10001010 Odd Parity ѧ 1 ʴ ԴҴԴ IC 74LS280 ҧѭҳ͡ CPU Դ Halt ʴҹҧ˹ҧ PARITY ERROR SYSTEM HALT
        ͧ Parity bit ªѡ ö͡Դ˹˹ ԴҴ ͡ԴҴ Դ ԴԴҴ 2 Ե 10001001 ¹ 10101011 öԴҴԸ Parity
        ҹͧ RAM ͧ RAM ѹ
        1. DIP (Dual In-line Package) ҹѹ DIP RAM ٻͧ IC (Integrate Circuit ) Memory chip ҹ Դ RAM ԴԴŧ ͤ絢ͧ DIP ͧԴ DIP ҡ ͧիͤҡ ͧ ˭ҡ Դ DIP ѧͧѴѧ Pin ͺҧ ѡ ѧ Դ
         2. SIPP (Single In-line Pin Package) ŴҡͧԴ RAM Ẻ DIP ŧ Դŧ PCB (Printed Circuit Board) С͹ SIPP PCB Pin ͹ͧ IC Pin ͧ SIPP §§ͧ PCB Դ SIPP ѡɳ§˹ӹǹҡ Pin ͧ SIPP Ѵ Դ¡ DIP ҡ
         3. SIMM (Single In-line Memory Module) ٻҧ˹ ¡Ѻ SIPP ҧ ǹ͡Ѻ ͤ ҡ Pin Ẻ Edge Connector ǧ§ ѹͺͧ PCB ѡɳ͹Ѻ ҧ Դ SIMM ºŧç ͹ ºŧ§ѹSIMM ҹҧ ͤ絷͡ SIMM Edge connector SIMM Ѵѭͧ˹ͧ Pin Ѻͤ
        SIMM ١Ե͡Դҧ ҧͧͧ SIMM Դ 8 Ե, 16 Ե, 32 Ե ѴҧѺͧ Edge connector ҵҹ ҧѹ
         4. DIMM (Dual In-line Memory Module) RAM Դ ١˹ ҵҹҧ JEDEC (Joint Electron Device Engineering Council) ѡɳ SIMM 168 Pin (ҧ 84 pin )


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