ʶһѵ¡ͧ CPU Z-80

çҧͧ CPU Z-80 çҧѲҡ 8080 ѧçҧҹ ͹ CPU 8080 ͧҡ Z-80 ѲҡҧͿ ֧´ҧաСѹ

ٻʴ block diagram ͧ CPU Z-80

çҧͧ Z-80 CPU Сͺ ըö ¹ҹ֧ 208 ¡ͧը좹Ҵ 8 Է 18 ըը좹Ҵ 16 Է ա 4 ը

ٻҾʴըͧ CPU Z-80

ըѡҹ

ըá A,F,B,C,D,E,H,L ը좹Ҵ 8Է ҹ ը öСͺѹը AF,BC,DE HL ըѺҹѡɳͧը Ҵ 16 Է á CPU Ҩ§ըը A Accumulator , F flag , flagͧ Z-80 ѹ 6 ֧§ 6 Է Z-80 Էա 2 Է ը F ը F Ѻ set , reset áҧ Եʵ ͨԡö F ͹ը˹ Ѻ A ը좹Ҵ 16Է

ٻҾʴըѡҹ

ըͧ

ըö ҡըѡ ը ش֧ѹ 8 A', F', B', C', D', E', H' ,L' ըը ͧըѡҹҧ͹ ѧը ֧öҧԵʵͨԡ

ٻҾʴըͧ

ըҹҧ

ҹ (PC - Program counter) ҹը좹Ҵ 16Է ˹˹ͧá

ҹҡʹʺѧ˹˹ CPU ҹҹҧѵѵ ѧáҡ CPU ѧ˹ (Jump) ʹ Ŵѧҹҧѵѵ
ᵤ· (SP - Stack pointer) ըҴ 16 ԷѺѧʹشͧᵤ RAM ǹͧᵤѡɳçҧ ˹ ѧ¡͡͹ (last in first out) ҨѺ push pop ҡ ըCPU ѡɳͧᵤѧ ǹá interrupt ¡ interrupt ͧҹѺѡѺҡ interrupt ѧѡҡᵤѺѧҹ ӹͧѹ áѧѹ ѧ áٻͧ interrupt ͧ ö ͹ѹش
Թതը (IX,IY - index register) CPU Z-80 Թതը좹ҹ 16 Է 2 ªѡ ˹ʹҹ (base address) ˹ҧʹẺԹതʹʫ (index addressing)ͧԹതʹ ԹതըѺԴҡѺա 8 Է ˹ʹѺ ԴҡѺ¡ displacement ٻͧŢ 2's complement
ԹѾྨʹը (I-Interrupt page address register) ԹѾ ͧ Z-80 ˹ԹѾͧ Z-80ԷҾ ٧ ԴԹѾ ѹöҧʹҧ ˹ ը Ѻҡػóա 8 Է ѧ˹Ŵ ǹ Ը֧öǹ˹
ըê˹ (R-memory reflesh register) ١Ѻ˹ ͡Ѻ˹Դ static Դ dynamic ͧ Ҥ١˹٧ Z-80 С˹ѹö ê˹ ҧѵѵ R ըա 1 ءá fetch ը R ١͡ѧʹʺ ǹԷӤѭѧͧѧѹѺ ѭҳ ê͡ ö˹Ѻ ը R ը ¡ҧç
ͤ (accumulator) š (flag) ٨ըѡ operand ѺҧԵʵͨԡ ըѡ§ 8 Է ¡ "ͤ (accumulator)" áǹͧ˹Եʵ ͨԡԴ͹ҧͧʴʶҹҾͧ͹

͹ѾٹѾǡźá ҧԵʵ ʴ͹ԵѾʴʶҹ š (flag) šը좹Ҵ 8 Է
öѺͤ ը좹Ҵ 16 Է ѧö͹ҡ ͤ A š F A' F' ҹ ͧ A F ԷҾ

ٻҾʴըҹҧ

˹ӹdzҧԵʵͨԡ (ALU - arithmetic and logic unit)

Ӥѭͧ CPUͧѧѺ˹ӹdzҧԵʵ ͨԡ (ALU) ǹ ALU Ҩҡ͡ CPU CPU ǹ ALU

ӤѭСͺ ǡ (add) , ź (subtract) , ͨԡ AND , ͨԡ OR , ͨԡ EX-OR , ºº (compare) , ͹Էҧ , (increment) , Ŵ (decrement) , 緺Է (set bit) , 緺Է (reset bit) , ͺԷ (test bit)

ٻҾʴҹͧ ALU

   Z-80 CPU ҹѡɳҹ ӤѭСͺ
¹ - ҹ˹
¹ - ҹػóԹط - ҷط
ͺʹͧԹѾ
ҹŢͧСͺǹҹͧѧӤѭ ࿷ (fetch) execute ǹͧ fetchСͺ state state state synchronize Ѻѭҳԡ

ͧҡСͺ machine cycle ѹ machine cycle öػ͡ҧ
1. š fetch (M1)
2. š¹ҹ˹
3. šѺԹطҷط
4. šͧ ͺʹͧ
5. šԹѾ ͺʹͧԹѾ
6. šѺԹѾẺ͹ʤ (Nonmaskable interrupt)
š࿷; (OCF - opcode fetch)
M1 áͧء M1 ѧࡵҡк ҹͧ CPU fetch ҡ program counter ŧѧ Address bus ѧҡ cycleͧѭҳ ԡ CPU ѭҳ /MREQ ѭҳ͡ CPU ͧԴ͡Ѻ˹ ѹ ѭҳ /RD ͡˹ ͧ /RDҹ ˹ Address ͧ ֧ŧͧ T2 CPU Ǩͺѭҳ ҧ /WAIT "0" ҹ /WAIT "0" CPU (WAIT state) Դ

ҹҡ˹ ѭҳ /MREQ /RD ҹ bus ҹ /MREQ OR /RD "0" CPU ѺԴ bus IR §(ٻ) ҡ bus IR º fetch ѭҳ /M1 "1" ͡ fetch ҧ /M1 cycle ѧ CPU ѭҳ refresh ˹ Դ䴹ԡ Address bus ͧ address ͧ refresh /RFSH ͧ͡ refresh ͧ

M1 cycle WAIT STATES

ء ŧͧ T2 Ǩͺ /WAIT "0" "0" CPU ҧ state /WAIT ա 1 cycle ѭҳ ѧ ء ŧͧ Tw Ǩͺ /WAIT աѹ

/WAIT "0" ҧ Tw ա ͧش CPU ҧѭҳ Tw ѭҳҧ ѧ ѭҳҧ A0-A15, /MREQ, /RD, /M1 /RFSH ŧͧ Tw
CPU Ǩͺѭҳ /WAIT ͨԡ "1" ѹ ҹҡ bus T3 T4

ªͧ Tw ˵״ҧѭҳҧ synchronous ҹѺػó͡ ͧҹ˹ ͧ״ѭҳ /RD /MREQ ͡Ǻ˹ ҧѭҳ /WAIT CPU ͧ

šҹ˹ (MR - memory read cycle) š¹˹ (MW - memory write cycle)

ҡٻ ʴ diagram ͧҹ¹˹ҹ¹˹ CPU 3 clock cycle T1,T2,T3

ҹ˹ CPU ʹͧҹ address bus A0-A15 ͹ ͹ áͧ machine cycle ѧҡѭҳ /MREQ /RD ͡ ءͧŧ ǧѧ T2 CPU

Ǩͺ /WAIT ͨԡ "0" CPU ҹ "0" ҧ Tw ǧѧ address bus ѭҳ /MREQ, /RD ѧ˹͡ҡ˹ŧ data bus CPU ѧҹ ѧҹͧ CPU Դѧŧͧ T3 ǧ ҹͧ CPU ͧѹҹԴҴ Դ˹ʹ ҹʹͧ
ӹͧѹѧͧ /MW ѹСͺ T1,T2 T3 (ó Tw) CPU ҧѭҳ /MREQ Ѻ /WR active ҧ CPU͡ data bus ͹ ҹ

pulse ¹ (/WR) ¹ (/WR) § ѧ bus º

óͧ˹ǧҹ machine cycle öҧ /WAIT "0" ŧͧ T2 CPU ҧ TwҺ /WAIT ѧ "0"

š¹ҷطҹԹط(PW-port write and PR-port read)

¹ҷطҹԹط¤֧Ѻ¹ҹ˹ͧ ¹ ѭҳ /MREQ /IORQ diagram ¹ҷط ҹԹطʴѧٻ

ҧѴºѺ¹ҹ˹ա˹ǹͧʹ ʴǹͧ A0-A7 ҹ CPU ҧ Tw á 1 ١ѵѵ /WAIT ǧѧ /IORQ CPU ҧ T2 CPUö Ǩͺѧ /WAIT ŧͧ T2 Ǩͺ /WAITԴ ѧͧ Tw ᷹ͧ ҡ /WAIT CPUҧѭҳ Tw ա

šͺʹͧ (BUS REQUEST and ACKNOWLEDGE CYCLE)

ҡٻ diagram ͧͺʹͧ ʹ ѭҳ ҧ /BUSRQ CPUǨͺ /BUSRQ ѭҳԡѧ ¹ҡ "0" "1" ѭҳ state شͧء Mcycle /BUSRQ ͤտ CPU ૷ address bus data bus ʶҹ ʵѭҳԡ١ CPU ѭҳͺѺ (/BUSAK) CPU Ǻػó͡ҨԸ DMA(direct memory access) Դҧػó I/O Ѻ˹ç ó CPU Ǻç óѡѺӹǹҡ ʹ CPU Ǩͺ /BUSRQ ء ൷ ѹ /BUSRQ "1" ѭҳԡ൷ /BUSAK = "1" ͡ԡ ǺԨ

ó CPU öͺʹͧԹѾ ԹѾ Ẻ /NMI /INT

šѺѭҳԹѾͺʹͧѭҳԹѾ (Interrupt request and acknowledge cycle)

ҡٻ ʴ diagram ͧԹѾ CPU, CPU Ǩͺѭҳ INT ء pulse ѭҳԡ١شͧءҧǨͺ Դҡ software DI

(Disable interrupt) ԹѾ flip-flop Ѻ૷ ͡ҡ ѭҳ /BUSRQ ͤտ ԹѾѺͺʹͧ ѹ ͺʹͧ /INT Դ CPU ҧʶҹ /M1
ʶҹͧ /M1 /IORQ ͤտ᷹ /MREQ ͺʹͧԹ- Ѿ͹ͧ /IORQ CPU ҹ 8 Է ǤѺ ԹѾҡ data bus ѧࡵ
ó CPU ҧѭҳ Tw ͧ൷ ҧ ѵѵ ҧ Tw ػó͡Ǩͺػóҧ ԹѾ ѴѺ Ӥѭ (priority) ͧѭҳԹѾ

ѧö൷ /WAIT ա CPU ػóǤ ͧ ԹѾ data bus

šͺʹͧԹѾẺ͹ԹѾ (Nonmaskable interrupt response)

ҡٻ diagram ͧͺʹͧԹѾẺ nonmaskable ֧ pulse ͧѭҳԡ١ش͹á CPUǨͺ /NMI /NMI ͤտ (=0) CPU latch ͺʹͧԹѾ ѹ ԹѾ

Ը CPU Ӥѭ٧ش ǹҧ software öͧѹ CPU ͺʹͧ ͺʹͧԴѹѧԹѾչ֧ó Ӥѭ ԹѾԸ
CPU program counter stack ૷ program counter 0066H ǹͧ˹ 0066H

Z-80 § 40 ѡ Z-80 óZ-80ͧСͺѺػóСͺ¡ҹ ǹͧѭҳºʹ ʢѭҳǺ Ѵҧ ʴѧٻ

´ͧҧ ʴѧ

A0 - A15
ʹ ѭҳ͡ҡͤտ high ҷطẺ൷ ʹѹ16ٵԴ͡Ѻ˹ ҡ֧ 216 = 64 K 亷͡ҡǹͧ

ʹѧ˹ 췢ͧػóԹط-ҷط١ǡѺԹطҷ ͧʹʺ 8 Էҧ (A0 - A7) ʴ췴ѧ֧ػóԹطҷط 28 = 256 ǧѭҳ ҡê (/RFSH) ʹʺ A0 - A7ʴʹͧ˹ Ѻáê
D0 - D7
ʢ (data bus) ѡɳкẺͧҧ Z-80 պʢ 8 ʢ ҧҹͧҧ ١Ѻ˹ ѺػóԹط-طԴҧػóԹط-ҷطѺ˹
/M1
(machine cycle one) ѡɳͤտͨԡ "0" /M1ǹ͡Һ ١ѧ;ͧ亷 ǹͧ /M1 ҧ鹢࿷亷ѡɳͧ; ͧ亷 CBH, DDH, EDH, FDH (H ֧ŢҹԺˡ) ͡ҡ /M1 ѧҧѭҳ Ѻ/IORQ ͡ʶҹͺѺԹѾ
/MREQ
(memory request) ѡɳ൷ ͨԡͤտ "0" ѭҳ ͡Һ ٵͧ¹ҹ˹ʹҡʹʺ
/IOREQ
(input output request) ҷطѡɳ൷ͨԡͤտ "0" ѭҳ͡ Һ ٵͧԴ ѺػóԹط-ҷط ʹʺ 8 Էҧʴǹʢʴ ҧ١Ѻ I/O ͡ҡ /IORQ ԴѺѭҳ /M1 ֧͡ʶҹ١ѧͺʹͧ ԹѾ ǹͧʢҹͧԹѾǤ
/RD
(memory read) ҷطͤտͨԡ "0" /RD ͡ ٵͧҹҡ˹ػó I/O
/WR
(memory write) ҷطẺͤտͨԡ "0" /WR
ѭҳ͡ ٵͧ¹¹˹ʹʺʡ˹Ҩ˹ػó I/O
/RFSH
(refesh) ҷطͤտͨԡ "0" /RFSH ѭҳ͡Һѭҳʹʺ ǹ A0 - A6 ʹê˹ Դ䴹ԡ ǹԷ A0 "0" ǹԷ A8 - A15 ʴͧը
/HALT (halt state) ҷطͤտͨԡ "0" ѭҳ /HALTʴ HALT شԹѾǧ HALT ٨ ͹ѧ NOP (no

operation) Դҹ ѭҳê˹Դ䴹ԡ
/WAIT
(wait) Թط ͤտͨԡ "0" /WAIT˹ʴ͡ ش óػó Թط-ҷط ˹öѺ ѹ /WAIT ԧաѺ

ػóԹطҷط ҹ
/INT
(interrupt request) Թط ͤտͨԡ "0" /INT ѭҳҧҡ ػóԹطҷطͧԹѾ ٨Ǩͺѭҳ ء áͺʹͧͧԹѾö Ǻ Ϳ

૷ԹѾԺͺ (IFF) ͺʹͧԹѾԴ ѧͧ /BUSRQ ͤտ ٵͺʹͧ ԹѾ ٨ҧѭҳͺҧѭҳ /IORQ ҧǧ /M1
ͺʹͧ ԹѾ¡ 3 Ẻ ͸ԺԹѾ
/NMI
(nonmaskable interrupt) Թطзԡ͡ͺū ŧԹѾ Ը ٨Ӥѭ٧ /INT ѹͺʹͧ ѹ ˹ 0066H

ѵѵ áó ٨ Ѻҹ ԹѾ
/RESET
(reset) Թطͤտͨԡ "0" óѧ
1. ͧ PC "0"
2. IFF Ѻ Disable
3. ը R 00H
4. ૷Թþ 0
ҧʹʺкʢѺá٧ ¡͡ҡ ǹѭҳ ǺѺ ѭҳͤ êԴ
/BUSRQ
(bus request) Թطͤտͨԡ "0" /BUSRQ ѭҳ͡Ѻ ͧ٤¤ʡǤͧٷʹкʢ ʶҹᴹ٧ ͧ¡͡ҡʹͧ
/BUSAK
(bus acknowledge) ҷط ͤտͨԡ "0" /BUSAK ѭҳͺҡ ¡ͧ͡ҡʹʺкʢº
CLK(clock) ѭҳԡ͹к

Z-80 ԹطѺԹѾ 2 ԹѾẺ (INT) ͹ (MNI)ѺԹѾẺ ö CPU ҹǹҧ ͧǹ ԹѾẺ͹ŹҧѺẺŤԹѾẺԴѹöشʹªͿ
͹ԹѾ(NON-MASKABLE INTERRUPT) ԹѾ͹ҧ NMI ͧ·ͨԡͧͤտԴͨԡ "0" Ѻѭҳ ٨Ѵ

ͺʹͧԹѾ¹ PC 0066H Դʹ ͺʹͧóͧ͹Ź ٶǹӤѭشͧҧͿǹöشԹѾ ԹѾԸ֧ѡó˵óӤѭش ҡѡͧԹѾ ͧ PC ٨ѡѺѡáѺ׹ѡ RETN (Return from Nonmaskable)
ԹѾẺ (Maskable Interrupt) ԹѾẺ ͧԹѾҹҧ INT ͧ Ѻѭҳ٨ǨͺʶҹͧͧͺʹͧѾ ͺʹͧöͿ ѧ֧ö˹ԹѾ ѺͺʹͧçǹͧԹѾԸö¡Ѿ͡ 3 ¡Ϳͧ ¡ 0 (IM0), 1 (IM1), 2 (IM2)
ԹѾ 0 ͡ Z-80 ͡ Z-80 ͺʹͧѭҳԹѾ͹ 8080 ءС ԹѾ ԴҧͿѺԹѾ 0 (IM0) šԹѾҹͧ٨ش Ѵ ͺѺԹѾѭҳͺѺ /M1 Ѻ /IORQ ҹ 1 亷 ҧʢ 1 亷Ѻҡ ػó I/O ԹѾ ҹ٨;ѹҹ Ҵ 1 亷

ԹѾ RST RST٨ PC ¹ PC ѡɳͧ RST ѧ٨ҹͧͧԹѾ
ͺʹͧԹѾѭҳ /M1 /IORQ ҡ I/O Ҩ I/O RST (亷) CALL
Ҵ 3 亷 I/O ͺѺ ԹѾ(/M1+/IORQ) CDH (CALL) Һ CALL ѧͧա 2 亷 ٨ҧչ ŵҹ˹͹ CALL ԧ ͧǧҧСͺ I/O ա 2 亷 ԹѾԸҨ˹෤Ԥҧѹͧ͡ؤ
ѷԹ͡ǺԹѾѴѺӤѭԹѾ IC 8214 ͺʹͧԹѾ /M1 /IORQ ͹á

ǧչ /M1 ٨ҹչ /M1 Tw ػó I/Oáǹહ (Daisy Chain) ѴѺӤѭͧԹѾ
ҧͿ IM1˹ѺԹѾ EI DIҹ͹ͧ 8080 ءС ѧѧҡ ٨ͧ 0 ѵѵ
ԹѾ 1ö˹ IM1 ԹѾ

͹ѹѺ͹ԹѾءСҧѹ§ʵ˹ 0038H (ó͹ 0066H) ӹǹҺ 1 ҡ͹ŷ
ٵͧ Tw ա 2 ൷ԹѾöͿ
ԹѾ 2 Z-80 մöǡѺԹѾ٧ҡ

ԹѾ˹ IM2 ٵͺʹͧѧѹ EI DI áѧٵͺʹͧԹѾ ó ʹá֧ 16 Է ԹѾдǡǴաҡ
ԸͺʹͧԹѾó ѭҳ /INT ٵǨͺ͹شͧ ٨ͺʹͧ /M1 Ѻ /IORQ ͡ ѭҳ /M1 Ѻ /IORQ ͡ػó
/INT Ҵ 1 亷ҧʢ Ѻҡ I/O Ҵ 1 亷ҧʢٶ Ǥͧ ԹѾ Է D0 ͧ "0" ǹԷ٨Ǥʹ亷ѭҡը 1 Ӥѭ٧ ¡ѧ˹ҹ˹ 2 亷ԴѹŴ PC ҧʹ PC Ẻҧͧ


Ѻóöը I I/O ǤСͺ֧͡ҧ˹ͧ ԸáѧԴ
ػóҹԹѾѹ Z-80PIO, Z-80CTC, Z-80SIO ϫػóԹöǤѺҧԷҾ
ԹѾٵ֧ͧ 19 ൷ 7 ൷
࿷Ǥ 6 ൷ PC ൷ 6 ҹҡ˹ѧ PC
дԹѾ ʶҹҾͺʹͧԹѾ ٨Ǩͺ IFF

ԹѾԺͺóͧ Z-80 տԺͺʴʶҹҾ ԹѾ 2 Է IFF1 IFF2 ͧԷѺͧҡáͧͧ
૷Ժͺ ѡ IFF1˹˹ʹšԹ-
Ѿ IFF2 ˹ѡͧ IFF1 ٷҧ૷ IFF1 IFF2 Ѻ ʴʶҹ "0" ͧ IFF1 ôšԹѾ IFF1
= "0" ѺԹѾҧ INT ૷ IFF ö EI ʶҹҾͧ IFF1 IFF2 ¹ŧͧҡáҧ ػѧҧҧҧ

ҡҧػ ˹Ũͧ૷Ժͺ IFF1ա˹ ԴԹѾٵǨͺ IFF1 ǨͺѺʹ ҧóǨͺҧԷԵ á LD A, I LD A, R ͧ IFF2 ѧԵš
ԹѾẺ NMI Դдŷѹ IFF1 ѹ Ѻ ҧԹѾẺ NMI ԹѾẺա ٨Ѻʶҹ͹ ԹѾẺ NMI (ʶҹô)Ѻѡ IFF2 ҧѺǨͺѹ ͹ NMI ҧ Ѻѡ RETN ʶҹѡ IFF1 ͺʹͧ /INT IFF1 IFF2 Ѻѹ ѧ INT ѭҳ /INT öѺͺ

ʹͧ EI /INT ֧Ѻͺʹͧͧ ǹ RETI IFF1 IFF2 Դ¹ŧ
ѺͺʹͧԹѾͧ ʹͧԹѾͧѡɳӤѭͧԨóͧ ͡Ѻػó I/O ҧҧ١ͧ
ػͺʹͧԴѺѧ
1. ػó I/O ѭҳԹѾ /INT ͨԡ "0"
2. CPU ͺʹͧԹѾ /M1 ͨԡ "0" ͹ػó I/O ѴǡѺǹѴѺ͹ /IORQҡ٨֧ /IORQ ѧ /M1ͧҡǧҧ˹ IEI IEO ͧáહ /IORQ ͡ I/O

IEI ͧػóͨԡ "1" I/O Ǥҧʢ ٨ /IORQ /M1 繾ūҹҧʢહ ػóԹѾ IEO ͨԡ "0" ͹
IEI ͧ͡Ǥҡ I/O
3. ԹѾ ػóI/O ͤտԹѾ ͧ IEI = 1 IEO = 0 ѧáԹѾ ʶҹͧ I/O ͧ ͧ á

RETI (ED 4D) ͡ػó I/O ҺԹѾ
IEO "1" ŵI/O Ӥѭ ѹͧ /INT, /NMI /BUSRQ
ҧҧѴѺҹ õͺԹѾẺ /INT /NMI ǹ /BUSRQ ѡɳҹʹѧ
1. Ǩͺ /INT /NMI ٨Ǩͺء شͧѭҳԡͧ
2. /BUSRQ ѺǨͺء ͹شͧչ
3. CPU DMA Ѻ /INT /NMI
4. ѴͺʹͧѺѧ /BUSRQ /NMI /INT


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